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| cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00330 rev. *k revised april 20, 2017 S34MS01G1 s34ms02g1 s34ms04g1 1-bit ecc, x8 and x16 i/o, 1.8v v cc slc nand flash for embedded distinctive characteristics ? density ? 1 gb / 2 gb / 4 gb ? architecture ? input / output bus width: 8 bits / 16 bits ? page size: ? 8 = 2112 (2048 + 64) bytes; 64 bytes is spare area ? 16 = 1056 (1024 + 32) words; 32 words is spare area ? block size: 64 pages ? 8 = 128 kb + 4 kb ? 16 = 64k + 2k words ? plane size: ? 1 gb / 2 gb: 1024 blocks per plane 8 = 128 mb + 4 mb 16 = 64m + 2m words ? 4 gb: 2048 blocks per plane 8 = 256 mb + 8 mb 16 = 128m + 4m words ? device size: ? 1 gb: 1 plane per device or 128 mb ? 2 gb: 2 planes per device or 256 mb ? 4 gb: 2 planes per device or 512 mb ? nand flash interface ? open nand flash interface (onfi) 1.0 compliant ? address, data, and commands multiplexed ? supply voltage ? 1.8-v device: vcc = 1.7 v ~ 1.95 v ? security ? one time programmable (otp) area ? hardware program/erase dis abled during power transition ? additional features ? 2 gb and 4 gb parts support multiplane program and erase commands ? supports copy back program ? 2 gb and 4 gb parts support multiplane copy back program ? supports read cache ? electronic signature ? manufacturer id: 01h ? operating temperature ? industrial: ?40 c to 85 c ? industrial plus: ?40 c to 105 c performance ? page read / program ? random access: 25 s (max) ? sequential access: 45 ns (min) ? program time / multiplane program time: 250 s (typ) ? block erase (S34MS01G1) ? block erase time: 2.0 ms (typ) ? block erase / multiplane er ase (s34ms02g1, s34ms04g1) ? block erase time: 3.5 ms (typ) ? reliability ? 100,000 program / erase cycles (typ) (with 1-bit ecc per 528 bytes ( 8) or 264 words ( 16)) ? 10-year data retention (typ) ? for one plane structure (1-gb density) ? block zero is valid and will be valid for at least 1,000 program- erase cycles with ecc ? for two plane structures (2-gb and 4-gb densities) ? blocks zero and one are valid and will be valid for at least 1,000 program-erase cycles with ecc ? package options ? pb-free and low halogen ? 48-pin tsop 12 x 20 x 1.2 mm ? 63-ball bga 9 x 11 x 1 mm
document number: 002-00330 rev. *k page 2 of 71 S34MS01G1 s34ms02g1 s34ms04g1 contents distinctive characteristics .................................................. 1 performance .......................................................................... 1 1. general description ..................................................... 3 1.1 logic diagram................................................................ 4 1.2 connection diagram ...................................................... 5 1.3 pin description............................................................... 6 1.4 block diagram................................................................ 7 1.5 array organization ......................................................... 8 1.6 addressing ..................................................................... 9 1.7 mode selection ............................................................ 12 2. bus operation ............................................................ 13 2.1 command input ........................................................... 13 2.2 address input............................................................... 13 2.3 data input .................................................................... 13 2.4 data output.................................................................. 13 2.5 write protect ................................................................ 13 2.6 standby........................................................................ 13 3. command set ............................................................. 14 3.1 page read ................................................................... 15 3.2 page program.............................................................. 15 3.3 multiplane program ? s34ms02g1 and s34ms04g1 16 3.4 page reprogram ? s34ms02g1 and s34ms04g1... 16 3.5 block erase.................................................................. 17 3.6 multiplane block erase ? s34ms02g1 and s34ms04g1 18 3.7 copy back program..................................................... 18 3.8 edc operation ? s34ms0 2g1 and s34ms04g1...... 19 3.9 read status register................................................... 21 3.10 read status enhanced ? s34ms02g1 and s34ms04g1 21 3.11 read status register field definition .......................... 22 3.12 reset............................................................................ 22 3.13 read cache ................................................................. 22 3.14 cache program............................................................ 23 3.15 multiplane cache program ? s34ms02g1 and s34ms04g1 ................................................................ 24 3.16 read id........................................................................ 25 3.17 read id2...................................................................... 27 3.18 read onfi signature ............ .............. .............. .......... 27 3.19 read parameter page ................................................. 28 3.20 one-time programmable (otp) entry ........................ 30 4. signal descriptions ................................................... 30 4.1 data protection and power on / off sequence ........... 30 4.2 ready/busy.................................................................. 31 4.3 write protect operation ............................................... 32 5. electrical characteristics .......................................... 33 5.1 valid blocks ................................................................. 33 5.2 absolute maximum ratings ...... ................................... 33 5.3 ac test conditions ...................................................... 33 5.4 ac characteristics ....................................................... 34 5.5 dc characteristics ....................................................... 35 5.6 pin capacitance.... .............. ............ ........... ........... ....... 35 5.7 program / erase characteristics ................................... 36 6. timing diagrams ......................................................... 37 6.1 command latch cycle.................................................. 37 6.2 address latch cycle ..................................................... 38 6.3 data input cycle ti ming................................................ 38 6.4 data output cycle timing (cle=l, we#=h, ale=l, wp#=h) ........................................................................ 39 6.5 data output cycle timing (edo type, cle=l, we#=h, ale=l).......................................................................... 39 6.6 page read operation ................................................... 40 6.7 page read operation (interrupted by ce#).................. 41 6.8 page read operation timing with ce# don?t care...... 42 6.9 page program operation .............................................. 42 6.10 page program operation timing with ce# don?t care. 43 6.11 page program operation with random data input ...... 43 6.12 random data output in a pa ge ............ .............. ......... 44 6.13 multiplane page program operation ? s34ms02g1 and s34ms04g1 ................................................................. 44 6.14 block erase operation .................................................. 45 6.15 multiplane block erase ? s34ms02g1 and s34ms04g1 46 6.16 copy back read with optiona l data readout .............. 47 6.17 copy back program operati on with random data input.. 47 6.18 multiplane copy back program ? s34ms02g1 and s34ms04g1 ................................................................. 48 6.19 read status register timing ........... ........... ........... ....... 49 6.20 read status enhanced timing .............. .............. ......... 50 6.21 reset operation timing ................................................ 50 6.22 read cache ............ .............. ........... ........... ........... ....... 51 6.23 cache program............................................................. 53 6.24 multiplane cache program ? s34ms02g1 and s34ms04g1 ................................................................. 54 6.25 read id operation timing .... ........... ........... ........... ....... 56 6.26 read id2 operation timing .... ............... .............. ......... 56 6.27 read onfi signature timing.. ............... .............. ......... 57 6.28 read parameter page timing ............... .............. ......... 57 6.29 otp entry timing ......................................................... 58 6.30 power on and data protecti on timing ......................... 58 6.31 wp# handling............................................................... 59 7. physical interface ....................................................... 60 7.1 physical diagram .......................................................... 60 8. system interface ......................................................... 62 9. error management ...................................................... 64 9.1 system bad block replacement................................... 64 9.2 bad block management.......... ............... .............. ......... 65 10. ordering information .................................................. 66 11. document history ....................................................... 67 document number: 002-00330 rev. *k page 3 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1. general description the cypress S34MS01G1, s34m s02g1, and s34ms04g1 series is offered in 1.8 v cc and v ccq power supply, and with 8 or 16 i/o interface. its nand cell provides the most cost-effective solution for the solid state mass stor age market. the memory is d ivided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. the page size f or 8 is (2048 + 64 spare) bytes; for 16 (1024 + 32) words. each block can be programmed and erased up to 100,000 cycles wi th ecc (error correction code) on. to extend the lifetime of nand flash devices, the implement ation of an ecc is mandatory. the chip supports ce# don't care function. this function allows the direct download of the code from the nand flash memory devi ce by a microcontroller, since the ce# transitions do not stop the read operation. the devices have a read cache feature that improves the read throughput for large file s. during cache reading, the devices load the data in a cache register while the previous data is transferred to the i/o buffers to be read. like all other 2-kb page nand flash devices, a pr ogram operation typically writes 2112 bytes ( 8), or 1056 words ( 16) in 250 s and an erase operation can typically be performe d in 2 ms (S34MS01G1) on a 128-kb block ( 8) or 64-kword block ( 16). in addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two bloc ks at a time (again, one per plane). the multiplane architecture allows pr ogram time to be reduced by 40% and erase time to be reduced by 50%. in multiplane operations, data in the page can be read out at 45 ns cycle time per byte. the i/o pins serve as the ports for co mmand and address input as well as data input/outpu t. this interface allows a reduced pin c ount and easy migration towards different densities, without any rearrangement of the footprint. commands, data, and addresses are asynchronously intro duced using ce#, we#, ale, and cle control pins. the on-chip program/erase controller autom ates all read, program, and erase functi ons including pulse repetition, where require d, and internal verification and margining of data. a wp# pin is av ailable to provide hardware protection against program and eras e operations. the output pin r/b# (open drain buffer) sig nals the status of the device during each operation. it identifies if the program/er ase/read controller is currently active. the use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor. in a syst em with multiple memories the r/b# pins can be connected all together to provide a global status signal. the reprogram function allows the optimiz ation of defective block management ? w hen a page program operation fails the data can be directly programmed in another page inside the same arra y section without the time consuming serial data insertion phase . the copy back operation automatically executes embedded error detection operation: 1-bit e rror out of every 528 bytes ( 8) or 264 words ( 16) can be detected. with this feature it is no longer ne cessary to use an external mechanism to detect copy back operation errors. multiplane copy back is also supported. data read out after c opy back read (both for single and multiplane cases) is allowed. in addition, cache program and multiplane cache program oper ations improve the programing throughput by programing data using the cache register. the devices provide two innovative features: page reprogram and multiplane page reprogram. the page reprogram re-programs one page. normally, this operation is performed after a failed page program operation. similarly, the multiplane page reprogram re- programs two pages in parallel, one per plane. the first page must be in the first plane while the second page must be in the s econd plane. the multiplane page reprogram operation is performed after a failed multiplane page program operation. the page reprogram and multiplane page reprogram guarantee improved performance, since data insertion can be omitted during re- program operations. note : the S34MS01G1 device does not support edc. document number: 002-00330 rev. *k page 4 of 71 S34MS01G1 s34ms02g1 s34ms04g1 the devices come with an otp (one time programmable) area, whic h is a restricted access area where sensitive data/code can be stored permanently. this security featur e is subject to an nda (non-disclosure agreem ent) and is, therefore, not described in t he data sheet. for more details, contact your nearest cypress sales office. 1.1 logic diagram figure 1.1 logic diagram device density (bits) number of planes number of blocks per plane edc support main spare S34MS01G1 128m x 8 64m x 16 4m x 8 2m x 16 1 1024 no s34ms02g1 256m x 8 128m x 16 8m x 8 4m x 16 2 1024 yes s34ms04g1 512m x 8 256m x 16 16m x 8 8m x 16 2 2048 yes table 1.1 signal names i/o7 - i/o0 (8) data input / outputs i/o8 - i/o15 (16) cle command latch enable ale address latch enable ce# chip enable re# read enable we# write enable wp# write protect r/b# read/busy vcc power supply vss ground nc not connected vcc vss wp# cle ale re# we# ce# i/o0~i/o7 r/b# document number: 002-00330 rev. *k page 5 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.2 connection diagram figure 1.2 48-pin tsop1 contact 8, 16 devices note: 1. these pins should be c onnected to power supply or ground (as designated) following the onfi specification, however they might not be bonded internally. figure 1.3 63-bga contact, 8 device (balls down, top view) note: 1. these pins should be c onnected to power supply or ground (as designated) following the onfi specification, however they might not be bonded internally. nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc vss nc nc nc i/o7 i/o6 i/o5 i/o4 nc vcc nc vcc vss nc vcc nc i/o3 i/o2 i/o1 i/o0 nc nc nc vss 12 13 37 36 25 48 1 24 nand flash tsop1 x8 x8 nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc x16 x16 vss i/o15 i/o14 i/o13 i/o7 i/o6 i/o5 i/o4 i/o12 vcc nc vcc vss nc vcc i/011 i/o3 i/o2 i/o1 i/o0 i/o10 i/o9 i/o8 vss (1) (1) (1) (1) f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc (1) nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss (1) nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc (1) nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc document number: 002-00330 rev. *k page 6 of 71 S34MS01G1 s34ms02g1 s34ms04g1 figure 1.4 63-bga contact, x16 device (balls down, top view) 1.3 pin description notes: 1. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current su rges from the power supply. the pcb track widths must be sufficient to carry the curre nts required during program and erase operations. 2. an internal voltage detector di sables all functions whenever v cc is below 1.1v to protect the device from any involuntary program/erase during power transitions. table 1.2 pin description pin name description i/o0 - i/o7 (8) inputs/outputs . the i/o pins are used for command input, address input, data input, and data output. the i/o pins float to high-z when the device is deselected or the outputs are disabled. i/o8 - i/o15 (16) cle command latch enable. this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latching of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable. this input controls the selection of the device. when the device is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs are latched on the rising edge of we#. re# read enable. the re# input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid t rea after the falling edge of re# which also increment s the internal column address counter by one. wp# write protect. the wp# pin, when low, provides hardware pr otection against undesired data modification (program / erase). r/b# ready busy . the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage . the v cc supplies the power for all the operations (read, program, erase). an internal lock circuit prevents the insertion of commands when v cc is less than v lko . vss ground. nc not connected. f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss nc nc nc nc h3 h4 h5 h6 h7 h8 v cc i/o14 i/o12 i/o10 i/o0 i/o8 b9 a9 nc nc a2 nc nc i/o15 i/o13 nc vcc nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc i/o11 i/o1 i/o9 k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc document number: 002-00330 rev. *k page 7 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.4 block diagram figure 1.5 functional block diagram address register/ counter controller command interface logic command register data register re# i/o buffer y decoder page buffer x d e c o d e r nand flash memory array wp# ce# we# cle ale i/o0~i/o7 (x8) i/o0~i/o15 (x16) 1024 mbit + 32 mbit (1 gb device) program erase hv generation 2048 mbit + 64 mbit (2 gb device) 4096 mbit + 128 mbit (4 gb device) document number: 002-00330 rev. *k page 8 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.5 array organization figure 1.6 array organization ? 8 figure 1.7 array organization ? x16 plane(s) 2048 bytes 64 bytes i/o [7:0] 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 plane = (128k + 4k) bytes x 1024 blocks page buffer 1024 blocks per plane 1022 1023 1 0 2 array organization(x8) for 1 gb and 2 gb devices there are 1024 blocks per plane for 4 gb device there are 2048 blocks per plane note : 2 gb and 4 gb devices have two planes plane(s) 1024 words i/o0~i/o15 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 plane = (64k + 2k) words x 1024 blocks page buffer 1024 blocks per plane 1022 1023 1 0 2 array organization(x16) for 1 gb and 2 gb devices there are 1024 blocks per plane for 4 gb device there are 2048 blocks per plane note : 2 gb and 4 gb devices have two planes 32 words document number: 002-00330 rev. *k page 9 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.6 addressing 1.6.1 S34MS01G1 notes: 1. cax = column address bit. 2. pax = page address bit. 3. bax = block address bit. 4. block address concatenated with page address = actual page address, also known as the row address. 5. i/o[15:8] are not used during the addr essing sequence and should be driven low. for the 8 address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18 - a27: block address for the x16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17 - a26: block address table 1.3 address cycle map ? 1 gb device bus cycle i/o [15:8] (5) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 8 1st / col. add. 1 ? a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 ? a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 ? a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (ba0) a19 (ba1) 4th / row add. 2 ? a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a25 (ba7) a26 (ba8) a27 (ba9) 16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4) a16 (pa5) a17 (ba0) a18 (ba1) 4th / row add. 2 low a19 (ba2) a20 (ba3) a21 (ba4) a22 (ba5) a23 (ba6) a24 (ba7) a25 (ba8) a26 (ba9) document number: 002-00330 rev. *k page 10 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.6.2 s34ms02g1 notes: 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane address = actual page address, also known as the row address. 6. i/o[15:8] are not used during the addr essing sequence and should be driven low. for the 8 address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multiplane operat ions) / block address (for normal operations) ? a19 - a28: block address for the 16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17: plane address (for multiplane operat ions) / block address (for normal operations) ? a18 - a27: block address table 1.4 address cycle map ? 2 gb device bus cycle i/o [15:8] (6) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 8 1st / col. add. 1 ? a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 ? a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 ? a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 ? a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 ? a28 (ba9) low low low low low low low 16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4) a16 (pa5) a17 (pla0) a18 (ba0) 4th / row add. 2 low a19 (ba1) a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a25 (ba7) a26 (ba8) 5th / row add. 3 low a27 (ba9) low low low low low low low document number: 002-00330 rev. *k page 11 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.6.3 s34ms04g1 notes: 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane address = actual page address, also known as the row address. 6. i/o[15:8] are not used during the addr essing sequence and should be driven low. for the 8 address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multiplane operat ions) / block address (for normal operations) ? a19 - a29: block address for the 16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17: plane address (for multiplane operat ions) / block address (for normal operations) ? a18 - a28: block address table 1.5 address cycle map ? 4 gb device bus cycle i/o [15:8] (6) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 8 1st / col. add. 1 ? a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 ? a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 ? a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 ? a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 ? a28 (ba9) a29 (ba10) low low low low low low 16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4) a16 (pa5) a17 (pla0) a18 (ba0) 4th / row add. 2 low a19 (ba1) a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a25 (ba7) a26 (ba8) 5th / row add. 3 low a27 (ba9) a28 (ba10) low low low low low low document number: 002-00330 rev. *k page 12 of 71 S34MS01G1 s34ms02g1 s34ms04g1 1.7 mode selection notes: 1. x can be v il or v ih . high = logic level high. low = logic level low. 2. wp# should be biased to cmos high or cmos low for stand-by mode. 3. during busy time in read, re# must be held high to prevent unintended data out. table 1.6 mode selection mode cle ale ce# we# re# wp# read mode command input high low low rising high x address input low high low rising high x program or erase mode command input high low low rising high high address input low high low rising high high data input low low low rising high high data output (on going) low low low high falling x data output (suspended) x x x high high x busy time in read x x x high high (3) x busy time in program x x x x x high busy time in erase x x x x x high write protect x x x x x low stand by x x high x x 0v / v cc (2) document number: 002-00330 rev. *k page 13 of 71 S34MS01G1 s34ms02g1 s34ms04g1 2. bus operation there are six standard bus operations that control the device: command input, address input, da ta input, data output, write protect, and standby. (see table 1.6 .) typically glitches less than 5 ns on chip enable, write enable, and read enable are ignored by the memory and do not affect bus operations. 2.1 command input the command input bus operation is used to give a command to the memory device. commands are accepted with chip enable low, command latch enable high, address latch enable low, and r ead enable high and latched on the rising edge of write enable. moreover, for commands that start a modify operation (p rogram/erase) the write protect pin must be high. see figure 6.1 on page 37 and table 5.4 on page 34 for details of the timing requirements. command codes are always applied on i/o7:0 regardless of the bus configuration (8 or 16). 2.2 address input the address input bus operation allows t he insertion of the memory address. for t he s34ms02g1 and s34ms04g1 devices, five write cycles are needed to input the addre sses. for the S34MS01G1, four write cycles are needed to input the addresses. if necessary, a 5th dummy address cycle can be issued to S34MS01G1, whic h will be ignored by the nand device without causing problems. addresses are accepted with chip enable low, a ddress latch enable high, command latch enable low, and read enable high and latched on the rising edge of write enable. more over, for commands that start a modify operation (program/erase ) the write protect pin must be high. see figure 6.2 on page 38 and table 5.4 on page 34 for details of the timing requirements. addresses are always applied on i/o7:0 regardless of the bus configuration (8 or 16). refer to table 1.3 through table 1.5 on page 11 for more detailed information. 2.3 data input the data input bus operation allo ws the data to be programmed to be sent to the device. the data insertion is serial and timed by the write enable cycles. data is accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 6.3 on page 38 and table 5.4 on page 34 for details of the timing requirements. 2.4 data output the data output bus operation allows data to be read from the memory array and to check the st atus register content, the edc register content, and the id data. data can be serially shifted out by toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figure 6.4 on page 39 to figure 6.22 on page 49 and table 5.4 on page 34 for details of the timings requirements. 2.5 write protect the hardware write protection is activated when the write protect pi n is low. in this condition, modify operations do not start and the content of the memory is not altered. the write protect pin is not latc hed by write enable to ensure the protection even during power up. 2.6 standby in standby, the device is dese lected, outputs are disabled, and power consumption is reduced. document number: 002-00330 rev. *k page 14 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3. command set table 3.1 command set command 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy supported on S34MS01G1 page read 00h 30h no yes page program 80h 10h no yes random data input 85h no yes random data output 05h e0h no yes multiplane program 80h 11h 81h 10h no no onfi multiplane program 80h 11h 80h 10h no no page reprogram 8bh 10h no no multiplane page reprogram 8bh 11h 8bh 10h no no block erase 60h d0h no yes multiplane block erase 60h 60h d0h no no onfi multiplane block erase 60h d1h 60h d0h no no copy back read 00h 35h no yes copy back program 85h 10h no yes multiplane copy back program 85h 11h 81h 10h no no onfi multiplane copy back program 85h 11h 85h 10h no no special read for copy back 00h 36h no no read edc status register 7bh yes no read status register 70h yes yes read status enhanced 78h yes no reset ffh yes yes read cache 31h no yes read cache enhanced 00h 31h no no read cache end 3fh no yes cache program (end) 80h 10h no yes cache program (start) / (continue) 80h 15h no yes multiplane cache program (start/continue) 80h 11h 81h 15h no no onfi multiplane cache program (start/continue) 80h 11h 80h 15h no no multiplane cache program (end) 80h 11h 81h 10h no no onfi multiplane cache program (end) 80h 11h 80h 10h no no read id 90h no yes read id2 30h-65h-00h 30h no yes read onfi signature 90h no yes read parameter page ech no yes one-time programmable (otp) area entry 29h-17h-04h-19h no yes document number: 002-00330 rev. *k page 15 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.1 page read page read is initiated by writing 00h and 30h to the command re gister along with five address cycles (four or five cycles for S34MS01G1). two types of operations are av ailable: random read and serial page read. random read mode is enabled when the page address is changed. all data within the selected page are transferred to the data registers. the system controller may det ect the completion of this data transfer (t r ) by analyzing the output of the r/b pin. once the data in a page is loaded into the data registers, they may be read out in 45 ns cycle time by sequenti ally pulsing re#. the repetitive high to lo w transitions of the re# signal makes the device output the data , starting from the selected column address up to the last column address. the device may output random data in a page instead of the sequential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address that follows ra ndom data output command. random data output can be performed as many times as needed. after power up, the device is in read mode, so 00h comm and cycle is not necessary to start a read operation. any operation othe r than read or random data output c auses the device to exit read mode. see figure 6.6 on page 40 and figure 6.12 on page 44 as references. 3.2 page program a page program cycle consists of a serial dat a loading period in which up to 2112 bytes (8) or 1056 words (16 ) of data may be loaded into the data register, followed by a nonvolatile pr ogramming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial da ta input command (80h), followed by the five cycle address inpu ts (four cycles for S34MS01G1) and then serial data. the words othe r than those to be programmed do not need to be loaded. the device supports random data input within a page. the column a ddress of next data, which will be entered, may be changed to the address that follows the random data i nput command (85h). random data input ma y be performed as many times as needed. the page program confirm command (10h) in itiates the programming process. the inte rnal write state cont roller automatically executes the algorithms and controls timings necessary for prog ram and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register commands (70h or 78h) may be issued to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b# output, or the status bit (i/o6) of the status register. only the read status commands (70h or 78h) or reset command are valid while programming is in progress. wh en the page program is complete, the write status bit (i/o0) may be checked. the internal write verify detects only errors for 1?s that are not successful ly programmed to 0?s. the co mmand register remains in read status command mode until another valid comm and is written to t he command register. figure 6.9 on page 42 and figure 6.11 on page 43 detail the sequence. the device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2 112 bytes (8) or 1056 words (16) in a single page program cycle. the number of consecutive partial page programming operati ons (nop) within the same page must not exceed the number indicated in table 5.7 on page 36 . pages may be programmed in any order within a block. users who use ?edc check? (for s34ms02g1 a nd s34ms04g1 only) in copy back must comply with some limitations related to data handling during one page program sequence. refer to section 3.8 on page 19 for details. if a page program operation is interrupted by hardware reset, po wer failure or other means, the host must ensure that the interrupted page is not used for further read ing or programming operations until the ne xt uninterrupted block erase is complete . document number: 002-00330 rev. *k page 16 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.3 multiplane program ? s34ms02g1 and s34ms04g1 the s34ms02g1 and s34ms04g1 devices support multiplane program, making it possible to program two pages in parallel, one page per plane. a multiplane program cycle consists of a double serial data loadi ng period in which up to 4224 bytes (8) or 2112 words (16) o f data may be loaded into the data register, followed by a nonvo latile programming period where the loaded data is programmed int o the appropriate cell. the serial data loading period begins with inputting the serial data input command (80h), followed by the five cycle address inputs and serial data for the 1st page. the address for this page must be in the 1st plane (pla0 = 0). the devic e supports random data input exactly the same as in the case of page program operation. the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). once it has be come ready again, the ?81h? command must be issued, followed by 2nd page address (5 cycles) and its serial data input. the address for this page must be in the 2nd plane (pla0 = 1). the program confirm command (10h) starts paralle l programming of both pages. figure 6.13 on page 44 describes the sequences using the legacy protocol. in th is case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. figure 6.14 on page 45 describes the sequences using the onfi protocol. for both addresses issued in this protocol, the bl ock address bits must be the same except for the bit(s) that s elect the plane. the user can check operation status by moni toring r/b# pin or reading the status register (command 70h or 78h). the read status register command is also available during dummy busy time (t dbsy ). in case of failure in either page program, the fail bit of the status register will be set. refer to section 3.9 on page 21 for further info. the number of consecutive partial page programming operati ons (nop) within the same page must not exceed the number indicated in table 5.7 on page 36 . pages may be programmed in any order within a block. if a multiplane program operation is interr upted by hardware reset, power failure or ot her means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are comp lete for the applicable blocks. 3.4 page reprogram ? s34ms02g1 and s34ms04g1 page program may result in a fail, which can be detected by read status register. in this event, the host may call page reprogr am. this command allows the reprogramming of th e same pattern of the last (failed) page into another memory location. the command sequence initiates with reprogram setup (8bh), followed by the fi ve cycle address inputs of the target page. if the target patt ern for the destination page is not changed compared to the last page, the program confirm c an be issued (10h) without any data input cycle, as described in figure 3.1 . figure 3.1 page reprogram sr[6] i/ox cycle type as defined for page program a a c1 i/ox sr[6] cycle type cmd addr addr addr 00h c2 r1 r3 page n din din din din cmd d0 d1 . . . dn 10h cmd dout 70h e1 fail ! page m cmd 10h tadl twb tprog twb tprog addr r2 addr cmd addr addr addr addr addr 8bh c1 c2 r1 r3 r2 document number: 002-00330 rev. *k page 17 of 71 S34MS01G1 s34ms02g1 s34ms04g1 on the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be issued before program confirm ?10h?, as described in figure 3.2 . figure 3.2 page reprogram with data manipulation the device supports random data input within a page. the column address of next data, which will be entered, may be changed to the address which follows the random data input command (85h). random data input may be operated multiple times regardless of how many times it is done in a page. the program confirm command (10h) initiate s the re-programming process. the inter nal write state controller automatically executes the algorithms and controls timi ngs necessary for program and verify, ther eby freeing the system controller for other tasks. once the program process starts, the read status register command may be issued to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b# output , or the status bit ( i/o6) of the status r egister. only the read status command and reset command are valid when programming is in progress. when the page program is complete, the write status bit (i/o0) may be checked. the internal write verify detect s only errors for 1?s that are not succes sfully programmed to 0?s. the command register remains in read stat us command mode until another va lid command is written to the command register. the page reprogram must be issued in the same plane as the page pr ogram that failed. in order to program the data to a differen t plane, use the page program operation inst ead. the multiplane page reprogram can re-p rogram two pages in parallel, one per plane. the multiplane page reprogram operation is performed af ter a failed multiplane page program operation. the command sequence is very similar to figure 6.13 on page 44 , except that it requires the page reprogram command (8bh) instead of 80h and 81h. if a page reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for further read ing or programming operations until the ne xt uninterrupted block erase is complete . 3.5 block erase the block erase operation is done on a block basis. block addre ss loading is accomplished in three cycles (two cycles for S34MS01G1) initiated by an erase setup command (60h). only t he block address bits are valid while the page address bits are ignored. the erase confirm command (d0h) following the block address loadi ng initiates the internal eras ing process. this two-step sequence of setup followed by the execution command ensures th at memory contents are not accidentally erased due to external noise conditions. at the rising edge of we# after the erase confirm command input, the internal write controller handles erase and erase verify. once the erase process starts, the read status register commands (70h or 78h) ma y be issued to read the status register. c1 iox sr[6] sr[6] cycle type i/ox cycle type as defined for page program a a cmd addr addr addr addr 80h c2 r1 r3 page n din din din din cmd d0 d1 . . . dn 10h cmd addr addr addr addr 8bh c1 c2 r1 r3 fail ! page m cmd 10h tadl twb tprog twb tprog cmd dout 70h e1 din din din din d0 d1 . . . dn tadl addr r2 addr r2 document number: 002-00330 rev. *k page 18 of 71 S34MS01G1 s34ms02g1 s34ms04g1 the system controller can detect the co mpletion of an erase by monitoring the r/b# output, or the status bit (i/o6) of the status register. only the read status commands (70h or 78h) and reset command are valid while erasing is in progress. when the erase operation is completed, the write status bit (i/o0) may be checked. figure 6.15 on page 45 details the sequence. if a block erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interr upted block is erased under continuous power conditions before that block can be trusted for further programming and reading operatio ns. 3.6 multiplane block erase ? s34ms02g1 and s34ms04g1 multiplane block er ase allows the erase of two blocks in parallel, one block per memory plane. the block erase setup command (6 0h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles each). as for block erase, d0h command makes embedded operation start. in this case, multiplane erase does not need any dummy busy time between 1st and 2nd block insertion. see table 5.7 on page 36 for performance information. for the multiplane block erase operation, the address of the first block must be within the first plane (pla0 = 0) and the address of the second block in the second plane (pla0 = 1). see figure 6.16 on page 46 for a description of the legacy protocol. in this case, the block address bits for the first plane are all zero and the second address issued selects th e block for both planes. figure 6.17 on page 46 describes the sequences using the onfi prot ocol. for both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. the user can check operation status by moni toring r/b# pin or reading the status register (command 70h or 78h). the read status register command is also available during dummy busy time (t dbsy ). in case of failure in either erase, the fail bit of the status register will be set. refer to section 3.9 on page 21 for further information. if a multiplane block erase operation is in terrupted by hardware reset, power failur e or other means, the host must ensure that the interrupted blocks are erased under continuous power conditions before those bl ocks can be trusted for further programming and reading operations. 3.7 copy back program the copy back feature is intended to quickl y and efficiently rewr ite data stored in one page without utilizing an external memo ry. since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved. the benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copi ed to the newly assigned free block. the operation for performing a copy back is a sequentia l execution of page-r ead (without mandato ry serial access) and copy back program with the address of destina tion page. a read operation with the ?35h? command and the address of the source page moves the whole page of data into the internal data register. as soon as the device returns to the r eady state, optional data read-out is allowed by toggling re# (see figure 6.18 on page 47 ), or the copy back program command (85h) with the address cycles of the destination page may be written. the program confirm command (10h) is required to actually begin programming. the source and the destination pages in the copy back program sequence must belong to the same device plane (same pla0 for s34ms02g1 and s34ms04g1). copy back read and copy back program for a given plane must be between odd address pages or between even address pages for t he device to meet the program time (t prog ) specification. copy back program may not meet this specification when copying from an odd address page (sourc e page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). the data input cycle for modifying a portion or multiple dist inct portions of the source page is allowed as shown in figure 6.19 on page 47 . as noted in section 1. on page 3 the device may include an automatic edc (for s34ms02g1 and s34ms04g1) check during the copy back operation, to detect single bit errors in edc units contained within the source page. more details on edc operation and limitations related to data input handling during one copy back program sequence are available in section 3.8 on page 19 . if a copy back program operation is interrupted by hardware rese t, power failure or other means, the host must en sure that the interrupted page is not used for further read ing or programming operations until the ne xt uninterrupted block erase is complete . document number: 002-00330 rev. *k page 19 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.7.1 multiplane copy back progr am ? s34ms02g1 and s34ms04g1 the device supports multiplane copy back program with exactl y the same sequence and limitations as the page program. multiplane copy back program must be preceded by two si ngle page copy back read command sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane). multiplane copy back cannot cross plane boundaries ? the contents of the source page of one device plane can be copied only to a destination page of the same plane. edc check is available also for multiplane copy back program only for s34ms02g1 and s34ms04g1. when ?edc check? is used in copy back, it must comply with so me limitations related to data handling during one multiplane copy back program sequence. please refer to section 3.8 on page 19 for details on edc operation. the multiplane copy back program sequence represented in figure 6.20 on page 48 shows the legacy protocol. in this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. figure 6.21 on page 49 describes the sequence using the onfi protocol. for both addresses issued in this protocol, the block address bits must be the same except for the bit(s) th at select the plane. if a multiplane copy back program operation is interrupted by har dware reset, power failure or other means, the host must ensur e that the interrupted pages are not used fo r further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. 3.7.2 special read for copy back ? s34ms02g1 and s34ms04g1 the s34ms02g1 and s34ms04g1 devices su pport special read for copy back. if copy back read (described in section 3.7 and section 3.7.1 on page 19 ) is triggered with confirm command ?36h? instead ? 35h?, copy back read from target page(s) will be executed with an increased internal (v pass ) voltage. this special feature is used in order to minimize the number of re ad errors due to over-program or read disturb ? it shall be u sed only if ecc read errors have occurred in the sour ce page using page read or copy back read sequences. excluding the copy back read confirm comm and, all other features described in section 3.7 and section 3.7.1 for standard copy back remain valid (including the figures referred to in those sections). 3.8 edc operation ? s34ms02g1 and s34ms04g1 error detection code check is a feature that can be used durin g the copy back operation (both single and multiplane) to detect single bit errors occurring in the source page(s). note : the S34MS01G1 device does not support edc. ? edc check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is composed of 512 bytes of main array and 16 bytes of spare area (see table 3.3 and table 3.4 on page 20 ). the described 528-byte area is called an ?edc unit.? ? in the x16 device, edc allows detection of up to 1 single bit error every 264 words, where each 264 word group is composed by 256 words of main array and 8 words of spare area see table 3.3 and table 3.4 on page 20 ). the described 264-word area is called ? edc unit. ? edc results can be checked through a specific read edc register command, available only after issuing a copy back program or a multiplane copy back program. the edc register can be queried during the copy back program busy time (t prog ). for the ?edc check? feature to operate correctly, specific conditions on data input handling apply for program operations. for the case of page program, multiplane page program, pa ge reprogram, multiplane page reprogram, cache program, and multiplane cache program operations: ? in section 3.2 on page 15 it was explained that a number of consecutive partial program o perations (nop) is allowed within the same page. in case this feature is used, the number of partial program operat ions occurring in the same edc unit must not exceed 1. in other words, page program operations must be performed on the whole page, or on whole edc unit at a time. ? ?random data input? in a given edc unit can be executed several times during one page program sequence, but data cannot be written to any column address more than once before the program is initiated. document number: 002-00330 rev. *k page 20 of 71 S34MS01G1 s34ms02g1 s34ms04g1 for the case of copy back program or multiplane copy back program operations: ? if random data input is applied in a given edc unit, the entire edc unit must be written to t he page buffer. in other words, the edc check is possible only if the whole edc unit is modified during one copy back program sequence. ? ?random data input? in a given edc unit can be execut ed several times during one copy back program sequence, but data insertion in each column address of the edc unit must not exceed 1. if you use copy back without edc check, none of the limitations described above apply. after a copy back program operation, the host can use read edc status register to check the status of both the program operation and the copy back read. if the edc was valid and an error was reported in the edc (see table 3.2 on page 20 ), the host may perform special read for copy back on the source page and attemp t the copy back program again. if this also fails, the host can execute a page read operation in order to correct a single bit error with external ecc software or hardware. 3.8.1 read edc status register ? s34ms02g1 and s34ms04g1 this operation is available only after issuing a copy back program and it allows the detection of errors during copy back read. in the case of multiplane copy back, it is not possible to know which of the two read operations caused the error. after writing the read edc status register command (7bh) to the command register , a read cycle outputs the content of the edc register to the i/o pins on the falling edge of ce# or re#, whichever occurs last. the operation is the same as the read status register command. refer to table 3.2 for specific edc register definitions: table 3.2 edc register coding id copy back program coding 0 pass / fail pass: 0; fail: 1 1 edc status no error: 0; error: 1 2 edc validity invalid: 0; valid: 1 3na ? 4na ? 5 ready / busy busy: 0; ready: 1 6 ready / busy busy: 0; ready: 1 7 write protect protected: 0; not protected: 1 table 3.3 page organization in edc units main field (2048 byte) spare field (64 byte) ?a? area (1st sector) ?b? area (2nd sector) ?c? area (3rd sector) ?d? area (4th sector) ?e? area (1st sector) ?f? area (2nd sector) ?g? area (3rd sector) ?h? area (4th sector) 8 512 byte 512 byte 512 byte 512 byte 16 byte 16 byte 16 byte 16 byte 16 256 words 256 words 256 words 256 words 8 words 8 words 8 words 8 words table 3.4 page organization in edc units by address sector main field (column 0-2047) spare field (column 2048-2111) area name column address area name column address 8 1st 528-byte sector a 0-511 e 2048-2063 2nd 528-byte sector b 512-1023 f 2064-2079 3rd 528-byte sector c 1024-1535 g 2080-2095 document number: 002-00330 rev. *k page 21 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.9 read status register the status register is used to retrieve th e status value for the last operation iss ued. after writing 70h command to the comman d register, a read cycle outputs the c ontent of the st atus register to the i/o pins on th e falling edge of ce# or re#, whichever occurs last. this two-line control allows the system to poll the progress of each device in multiple memory connections even when r/b# pins are common-wired. refer to section 3.5 on page 22 for specific status register definition, and to figure 6.22 on page 49 for timings. if the read status register command is issued during multiplane operations then status regist er polling will return the combine d status value related to the outcom e of the operation in the two planes according to the following table: in other words, the status register is dynamic; the user is not require d to toggle re# / ce# to update it. the command register remains in status read mode until further co mmands are issued. therefore, if the status register is read during a random read cycle, the read command (00h) must be issued before starting read cycles. note: the read status register command sh all not be used for concurrent operations in multi-die stack configurations (single ce #). ?read status enhanced? shall be used instead. 3.10 read status enhanced ? s34ms02g1 and s34ms04g1 read status enhanced is used to retrieve the status value for a previous operation in the specified plane. figure 6.23 on page 50 defines the read status enhanced behavior and timing s. the plane and die address must be specified in the command sequence in order to retrieve the status of the die and the plane of interest. refer to table 3.5 for specific status register defi nitions. the command register remain s in status read mode until further commands are issued. the status register is dynamic; the user is not required to toggle re# / ce# to update it. 4th 528-byte sector d 1536-2047 h 2096-2111 16 1st 256-word sector a 0-255 e 1024-1031 2nd 256-word sector b 256-511 f 1032-1039 3rd 256-word sector c 512-767 g 1040-1047 4th 256-word sector d 768-1023 h 1048-1055 status register bit composite status value bit 0, pass/fail or bit 1, cache pass/fail or table 3.4 page organization in edc units by address sector main field (column 0-2047) spare field (column 2048-2111) area name column address area name column address 8 document number: 002-00330 rev. *k page 22 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.11 read status register field definition table 3.5 below lists the meaning of each bit of the read stat us register and read status enhanced (s34ms02g1 and s34ms04g1). 3.12 reset the reset feature is executed by writing ffh to the command register. if the device is in the busy state during random read, program, or erase mode, the reset operation will abort these opera tions. the contents of memory cells being altered are no long er valid, as the data may be partially programmed or erased. the co mmand register is cleared to wait for the next command, and the status register is cleared to value e0h w hen wp# is high or value 60h when wp# is lo w. if the device is al ready in reset state a new reset command will not be accepted by the command register. the r/b# pin transitions to low for t rst after the reset command is written. refer to figure 6.24 on page 50 for further details. the status register can al so be read to determine the status of a reset operation. 3.13 read cache read cache can be used to increase the read operation speed, as defined in section 3.1 on page 15 , and it cannot cross a block boundary. as soon as the user starts to read one page, the devi ce automatically loads the next page into the cache register. se rial data output may be executed while data in the memory is read into the cache regist er. read cache is initiated by the page read sequence (00-30h) on a page m. after random access to the first page is complete (r/b# returned to high, or read status register i/o6 switches to high), two command sequences can be used to continue read cache: ? read cache (command ?31h? only): once the command is latched into the command register (see figure 6.26 on page 51 ), device goes busy for a short time (t cbsyr ), during which data of the first page is tr ansferred from the data register to the cache register. at the end of this phase, the cache register data can be output by toggling re# while the next page (page address m+1) is read from the memory array into the data register. ? read cache enhanced (sequence ?00h? document number: 002-00330 rev. *k page 23 of 71 S34MS01G1 s34ms02g1 s34ms04g1 subsequent pages are read by issuing additional read cache or read cache enhanced command sequences. if serial data output time of one page exceeds random access time (t r ), the random access time of the next page is hidden by data downloading of the previous page. on the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long a s needed to complete random access to this page, transfer its cont ents into the cache register, and trigger the random access to the following page. to terminate the read cache operation, 3fh command should be issued (see figure 6.28 on page 52 ). this command transfers data from the data register to the cach e register without issuing next page read. during the read cache operation, the device doesn't allow any other co mmand except for 00h, 31h, 3fh, read sr, or reset (ffh). to carry out other operations, read cache must be terminated by the read cache end command (3fh) or the device must be reset by issuing ffh. read status command (70h) may be issued to check the status of the different registers and the busy/ready status of the cached read operations. ? the cache-busy status bit i/o6 indicates when th e cache register is r eady to output new data. ? the status bit i/o5 can be used to determine when the cell reading of the current data register contents is complete. note : the read cache and read cache end commands reset the column c ounter, thus, when re# is togg led to output the data of a given page, the first output data is related to the first by te of the page (column address 00h). random data output command c an be used to switch column address. 3.14 cache program cache program can improve the program th roughput by using the cache register. th e cache program operation cannot cross a block boundary. the cache register allows new data to be input wh ile the previous data that was transferred to the data registe r is programmed into the memory array. after the serial da ta input command (8 0h) is loaded to the co mmand register, followed by five cycles of address, a full or part ial page of data is latched into the cache register. once the cache write command (15h) is loade d to the command register, t he data in the cache register is transferred into the da ta register for cell programming. at this time the de vice remains in the busy state for a short time (t cbsyw ). after all data of the cache register is transferred into the data regi ster, the device returns to the ready state and allows loading the next data into the cache register through another cache program command sequence (80h-15h). the busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data register. cell programming the data of the data register and lo ading of the next data into the cache register is consequently processed through a pipeline model. in case of any subsequent sequence 80h - 1 5h, transfer from the cache register to th e data register is held off until cell prog ramming of current data register contents is complete; till this moment t he device will stay in a busy state (t cbsyw ). read status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the cached program operations. ? the cache-busy status bit i/o6 indicates when th e cache register is r eady to accept new data. ? the status bit i/o5 can be used to determine when the cell programming of the current data register contents is complete. ? the cache program error bit i/o1 can be used to identif y if the previous page (page n-1) has been successfully programmed or not in a cache program operation. the st atus bit is valid upon i/o6 status bit changing to 1. ? the error bit i/o0 is used to identify if any error has been detected by the program/erase controller while programming page n. the status bit is valid upon i/o5 status bit changing to 1. i/o1 may be read together with i/o0. if the system monitors the progress of the operation only with r/b#, the last page of the target program sequence must be programmed with page program confirm command (10h). if the cache program command (15h) is used instead, the status bit i/o5 must be polled to find out if the last programming is finished before starting any other operation. see table 3.5 on page 22 and figure 6.29 on page 53 for more details. document number: 002-00330 rev. *k page 24 of 71 S34MS01G1 s34ms02g1 s34ms04g1 if a cache program operation is interrupted by hardware reset, po wer failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are comp lete for the applicable blocks. 3.15 multiplane cache program ? s34ms02g1 and s34ms04g1 the multiplane cache program enables high program throughput by programming two pages in parallel, while exploiting the data and cache registers of both planes to implement cache. the command sequence can be summarized as follows: ? serial data input command (80h ), followed by the five cycle address inputs and then serial data fo r the 1st page. address for this page must be within 1st plane (pla0 = 0). the data of 1st page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. ? the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). ? once device returns to ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. address for this page mu st be within 2nd plane (pla0 = 1). the data of 2nd page other than those to be programmed do not need to be loaded. ? cache program confirm command (15h). once the cache write co mmand (15h) is loaded to the command register, the data in the cache registers is transferred into the data registers fo r cell programming. at this time the device remains in the busy state for a short time (t cbsyw ). after all data from the cache registers are transferred into the data registers, the device returns to the ready state, and allows loading the next dat a into the cache register through another cache program command sequence. the sequence 80h-...- 11h...-...81h...-...15h can be it erated, and each time the device will be busy for the t cbsyw time needed to complete programming the current data register contents, and tr ansferring the new data from the cache registers. the sequence t o end multiplane cache program is 80h-...- 11h...-...81h...-...10h. the multiplane cache program is available only within two paired blocks in separate planes. figure 6.30 on page 54 shows the legacy protocol for the multiplane cache prog ram operation. in this case, the block a ddress bits for the first plane are all ze ro and the second address issu ed selects the block for both planes. figure 6.31 on page 55 shows the onfi protocol for the multiplane cache program operation. for both addresses i ssued in this protocol, the block address bits must be the same except for the bit (s) that select the plane. the user can check operation stat us by r/b# pin or read status register comma nds (70h or 78h). if the user opts for 70h, read status register will provide ?global? info rmation about the operation in the two planes. ? i/o6 indicates when both cache registers are ready to accept new data. ? i/o5 indicates when the cell programming of the curr ent data registers is complete. ? i/o1 identifies if the previous pages in both planes (pages n-1) have been successf ully programmed or no t. this status bit is valid upon i/o6 status bit changing to 1. ? i/o0 identifies if any error has been detected by the prog ram/erase controller while programming the two pages n. this status bit is valid upon i/o5 status bit changing to 1. see table 3.5 on page 22 for more details. if the system monitors the progre ss of the operation only wi th r/b#, the last pages of the target program sequence must be programmed with page program confirm command (10h). if the cache program command (15h) is used instead, the status bit i/o5 must be polled to find out if the last programming is finished before starting any other operation. refer to section 3.9 on page 21 for further information. if a multiplane cache program operation is interrupted by hardware reset, power failure or other means, the host must ensure th at the interrupted pages are not used for furt her reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. document number: 002-00330 rev. *k page 25 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.16 read id the device contains a product id entification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. note : if you want to execute read status command (0x70) after read id sequence, you should input dummy command (0x00) before read status command (0x70). for the s34ms02g1 and s34ms04g1 devices, five read cycles se quentially output the manufactur er code (01h), and the device code and 3rd, 4th, and 5th cycle id, respectively. for the s34m s01g1 device, four read cycles sequentially output the manufactu rer code (01h), and the device code and 80h, 4th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 6.32 on page 56 shows the operation sequence, while table 3.6 to table 3.11 explain the byte meaning. table 3.6 read id for supported configurations density org v cc 1st 2nd 3rd 4th 5th 1 gb 8 1.8 v 01h a1h 00h 15h ? 2 gb 01h aah 90h 15h 44h 4 gb 01h ach 90h 15h 54h 1 gb 16 01h b1h 00h 55h ? 2 gb 01h bah 90h 55h 44h 4 gb 01h bch 90h 55h 54h table 3.7 read id bytes device identifier byte description 1st manufacturer code 2nd device identifier 3rd internal chip number, cell type, etc. 4th page size, block size, spare size, serial access time, organization 5th (s34ms02g1, s34ms04g1) ecc, multiplane information document number: 002-00330 rev. *k page 26 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3 rd id data 4 th id data table 3.8 read id byte 3 description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2-level cell 4-level cell 8-level cell 16-level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 11 interleave program between multiple chips not supported supported 0 1 cache program not supported supported 0 1 table 3.9 read id byte 4 description ? S34MS01G1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (without spare area) 1 kb 2 kb 4 kb 8 kb 0 0 0 1 1 0 1 1 block size (without spare area) 64 kb 128 kb 256 kb 512 kb 0 0 0 1 1 0 1 1 spare area size (byte / 512 byte) 8 16 0 1 serial access time 45 ns 25 ns reserved reserved 0 0 1 1 0 1 0 1 organization 8 0 16 1 document number: 002-00330 rev. *k page 27 of 71 S34MS01G1 s34ms02g1 s34ms04g1 5 th id data 3.17 read id2 the device contains an alternate identifica tion mode, initiated by writ ing 30h-65h-00h to the command register, followed by add ress inputs, followed by command 30h. the address for S34MS01G1 will be 00h-02h-02h-00h. the address for s34ms02g1 and s34ms04g1 wi ll be 00h-02h-02h-00h-00h. the id2 data can then be read from the device by pulsing re#. the command register remain s in read id2 mode until further commands are issued to it. figure 6.33 on page 56 shows the read id2 command sequence. read id2 values are all 0xfs, unless specific values are requested when ordering from cypress. 3.18 read onfi signature to retrieve the onfi signature, the comman d 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an address of 00h and read 36 bytes to get the onfi signature). the onfi signature is th e ascii encoding of 'onfi' where 'o' = 4fh , 'n' = 4eh, 'f' = 46h, and 'i' = 49h. reading bey ond four bytes yields indeterminate values. figure 6.34 on page 57 shows the operation sequence. table 3.10 read id byte 4 description ? s34ms02g1 and s34ms04g1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (without spare area) 1 kb 2 kb 4 kb 8 kb 0 0 0 1 1 0 1 1 block size (without spare area) 64 kb 128 kb 256 kb 512 kb 0 0 0 1 1 0 1 1 spare area size (byte / 512 byte) 8 16 0 1 serial access time 50 ns / 30 ns 25 ns reserved reserved 0 1 0 1 0 0 1 1 organization 8 0 16 1 table 3.11 read id byte 5 description ? s34ms02g1 and s34ms04g1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare area) 64 mb 128 mb 256 mb 512 mb 1 gb 2 gb 4 gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 reserved 0 0 0 document number: 002-00330 rev. *k page 28 of 71 S34MS01G1 s34ms02g1 s34ms04g1 3.19 read parameter page the device supports the onfi read parameter page operation, initiated by writing ech to the command register, followed by an address input of 00h. the host may monitor the r/b# pin or wait for the maximum data transfer time (t r ) before reading the parameter page data. the command register remains in paramete r page mode until further commands ar e issued to it. if the status register is read to determine when the data is ready, the re ad command (00h) must be issu ed before starti ng read cycles. figure 6.35 on page 57 shows the operation sequence, while table 3.12 explains the parameter fields. for x16 devices, the upper eight i/os are not used and are 0xff. note: for 41 nm 2 gb/4 gb cypress nand, for a particular conditi on, the read parameter page command does not give the correct values. to overcome this issue, the host must issue a re set command before the read parameter page command. issuance of reset before the read paramete r page command will provide the correct va lues and will not output 00h values. this does not apply to 48 nm 1 gb. table 3.12 parameter page description (sheet 1 of 3) byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, ?o? byte 1: 4eh, ?n? byte 2: 46h, ?f? byte 3: 49h, ?i? 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd to even page copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width S34MS01G100 (8) : 14h, 00h s34ms02g100 (8) : 1ch, 00h s34ms04g100 (8) : 1ch, 00h S34MS01G104 (16) : 15h, 00h s34ms02g104 (16) : 1dh, 00h s34ms04g104 (16) : 1dh, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports read status enhanced 2 1 = supports get features and set features 1 1 = supports read cache commands 0 1 = supports page cache program command S34MS01G1: 13h, 00h s34ms02g1: 1bh, 00h s34ms04g1: 1bh, 00h 10-31 reserved (0) 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 53h, 50h, 41h, 4eh, 53h, 49h, 4fh, 4eh, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) S34MS01G1: 53h, 33h, 34h, 4dh, 53h, 30h, 31h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h s34ms02g1: 53h, 33h, 34h, 4dh, 53h, 30h, 32h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h s34ms04g1: 53h, 33h, 34h, 4dh, 53h, 30h, 34h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 m jedec manufacturer id 01h 65-66 o date code 00h document number: 002-00330 rev. *k page 29 of 71 S34MS01G1 s34ms02g1 s34ms04g1 67-79 reserved (0) 00h memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 40h, 00h 86-89 m number of data bytes per partial page 00h, 02h, 00h, 00h 90-91 m number of spare bytes per partial page 10h, 00h 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logical unit (lun) S34MS01G1: 00h, 04h, 00h, 00h s34ms02g1: 00h, 08h, 00h, 00h s34ms04g1: 00h, 10h, 00h, 00h 100 m number of logical units (luns) 01h 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles S34MS01G1: 22h s34ms02g1: 23h s34ms04g1: 23h 102 m number of bits per cell 01h 103-104 m bad blocks maximum per lun S34MS01G1: 14h, 00h s34ms02g1: 28h, 00h s34ms04g1: 50h, 00h 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 01h, 03h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 reserved 0 1 = partial page programming has constraints 00h 112 m number of bits ecc correctability 01h 113 m number of interleaved address bits 4-7 reserved (0) 0-3 number of interleaved address bits S34MS01G1: 00h s34ms02g1: 01h s34ms04g1: 01h 114 o interleaved operation attributes 4-7 reserved (0) 3 address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 overlapped / concurrent interleaving support S34MS01G1: 00h s34ms02g1: 04h s34ms04g1: 04h 115-127 reserved (0) 00h electrical parameters block 128 m i/o pin capacitance 0ah 129-130 m timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 03h, 00h table 3.12 parameter page description (sheet 2 of 3) byte o/m description values document number: 002-00330 rev. *k page 30 of 71 S34MS01G1 s34ms02g1 s34ms04g1 note: 1. o? stands for optional, ?m? for mandatory. 3.20 one-time program mable (otp) entry the device contains a one-time programmable (otp) area, which is accessed by writing 29h-17h-04h-19h to the command register. the device is then ready to accept page re ad and page program commands (refer to page read and page program on page 15 ). the otp area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3fh are allowed. the host must issue the reset command (refer to reset on page 22 ) to exit the otp area and access the normal flash array. the block erase command is not allowed in the otp area. refer to figure 6.36 on page 58 for more detail on the otp entry command sequence. note : the otp feature in the S34MS01G1 do es not have nonvolatile protection. 4. signal descriptions 4.1 data protection and power on / off sequence the device is designed to offer protection from any involuntar y program/erase during power-transitions. an internal voltage det ector disables all functions whenever v cc is below about 1.1v. the power-up and power-down sequence is shown in figure 6.37 on page 58 , in this case v cc and v ccq on the one hand (and v ss and v ssq on the other hand) are shorted together at all times. the ready/busy signal shall be valid within 100 s after the power supplies have reached the minimum values (as specified on), and shall return to one within 5 ms (max). 131-132 o program cache timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 03h, 00h 133-134 m t prog maximum page program time (s) bch, 02h 135-136 m t bers maximum block erase time (s) S34MS01G1: b8h, 0bh s34ms02g1: 10h, 27h s34ms04g1: 10h, 27h 137-138 m t r maximum page read time (s) 19h, 00h 139-140 m t ccs minimum change column setup time (ns) 64h, 00h 141-163 reserved (0) 00h vendor block 164-165 m vendor specific revision number 00h 166-253 vendor specific 00h 254-255 m integrity crc S34MS01G100 (8) : 81h, 4fh s34ms02g100 (8) : 45h, e9h s34ms04g100 (8) : 3bh, a2h S34MS01G104 (16) : f3h, 39h s34ms02g104 (16) : 37h, 9fh s34ms04g104 (16) : 49h, d4h redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundant parameter pages ffh table 3.12 parameter page description (sheet 3 of 3) byte o/m description values document number: 002-00330 rev. *k page 31 of 71 S34MS01G1 s34ms02g1 s34ms04g1 during this busy time, the device executes the initializa tion process (cam reading), and dissipates a current i cc0 (30 ma max), in addition, it disregards all commands e xcluding read status register (70h). at the end of this busy time, the device defaults into ?read se tup?, thus if the user decides to issue a page read command, the 00h command may be skipped. the wp# pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before the internal ci rcuit gets ready for any command sequences as shown in figure 6.37 on page 58 . the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy the ready/busy output provides a method of indicating the completion of a page progra m, erase, copyback, or read completion. the r/b# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operation). it re turns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/b# outputs to be or-tied. because the pull-up resistor value is related to t r (r/b#) and the current drain during busy (ibusy) and output load capacitance is related to t f , an appropriate value can be obtain ed with the reference chart shown in figure 4.1 . figure 4.1 ready/busy pin electrical application rp vs. t r , t f and rp vs. ibusy rp ibusy busy ready v cc v oh v ol v ol : 0.1v, v oh - 0.1v vcc gnd device open drain output r/b# c l 200n 100n = t f (ns) 15 15 15 15 30 = t r (ns) 2m 1m ibusy [a] t r ,t f [s] = ibusy ( ma ) 0.9 1.7 60 90 120 0.6 0.4 rp (ohm) @ vcc = 1.8v, ta = 25c, c l =30 pf rp value guidence rp (min.) = = vcc (max.) - v ol (max.) 1.85v 3ma + i l i ol + i l rp(max) is determined by maximum permissible limit of tr. where is the sum of the input currents of all devices tied to the r/b# pin. l i t f t r legend 1k 2k 3k 4k : v cc document number: 002-00330 rev. *k page 32 of 71 S34MS01G1 s34ms02g1 s34ms04g1 4.3 write protect operation erase and program operations are ab orted if wp# is driven low during busy time, and kept low for about 100 ns. switching wp# low during this time is equivalent to i ssuing a reset command (ffh). the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the r/b# pin will stay low for t rst (similarly to figure 6.24 on page 50 ). at the end of this time, the command register is ready to process the next command, and the status register bit i/o6 will be cleared to 1, while i/ o7 value will be related to the wp# value. ref er to table 3.5 on page 22 for more information on device status. erase and program operations are enabled or disabled by setting wp# to high or low respective ly, prior to i ssuing the setup commands (80h or 60h). the level of wp# shall be set t ww ns prior to raising the we# pin for the set up command, as explained in figure 6.38 and figure 6.39 on page 59 . figure 4.2 wp# low timing requirements duri ng program/erase command sequence we# i/o[7:0] wp# valid > 100 ns sequence aborted document number: 002-00330 rev. *k page 33 of 71 S34MS01G1 s34ms02g1 s34ms04g1 5. electrical characteristics 5.1 valid blocks 5.2 absolute maximum ratings notes: 1. except for the rating ?operating temperature range?, stresses above those listed in the table absolute maximum ratings ?absolute maximum ratings? may cause permanent damage to the device. these are st ress ratings only and operation of the devic e at these or any other conditions abov e those indicated in the operating sections of this specification is not implied. exposure to ab solute maximum rating conditions for extended periods may affect d evice reliability. 2. minimum voltage may undershoot to -2v during transit ion and for less than 20 ns during transitions. 3. maximum voltage may overshoot to v cc +2.0v during transition and for less than 20 ns during transitions. 5.3 ac test conditions table 5.1 valid blocks device symbol min typ max unit S34MS01G1 n vb 1004 ? 1024 blocks s34ms02g1 n vb 2008 ? 2048 blocks s34ms04g1 n vb 4016 ? 4096 blocks table 5.2 absolute maximum ratings parameter symbol value unit ambient operating temperature (industrial temperature range) t a -40 to +85 c temperature under bias t bias -50 to +125 c storage temperature t stg -65 to +150 c input or output voltage v io (2) -0.6 to +2.7 v supply voltage v cc -0.6 to +2.7 v table 5.3 ac test conditions parameter value input pulse levels 0.0 v to v cc input rise and fall times 5 ns input and output timing levels v cc / 2 output load (1.7v - 1.95v) 1 ttl gate and c l = 30 pf document number: 002-00330 rev. *k page 34 of 71 S34MS01G1 s34ms02g1 s34ms04g1 5.4 ac characteristics notes: 1. the time to ready depends on the value of the pull-up resistor tied to r/b# pin. 2. if reset command (ffh) is written at ready stat e, the device goes into busy for maximum 5 s. 3. ce# low to high or re# low to high can be at different times and produce three cases. depending on which signal comes high fi rst, either t coh or t rhoh will be met. 4. during data output, t cea depends partly on t cr (ce# low to re# low). if t cr exceeds the minimum value specified, then the maximum time for t cea may also be exceeded (t cea = t cr + t rea ). 5. t rloh is only relevant for edo timing (t rc < 30 ns), which does no t apply for this device. table 5.4 ac characteristics parameter symbol min max unit ale to re# delay t ar 10 ? ns ale hold time t alh 10 ? ns ale setup time t als 25 ? ns address to data loading time t adl 100 ? ns ce# access time t cea (4) ?45ns ce# low to re# low t cr 10 ? ns ce# hold time t ch 10 ? ns ce# high to output high-z t chz ?30ns cle hold time t clh 10 ? ns cle to re# delay t clr 10 ? ns cle setup time t cls 25 ? ns ce# high to output hold t coh (3) 15 ? ns ce# high to ale or cle don't care t csd 10 ? ns ce# setup time t cs 35 ? ns data hold time t dh 10 ? ns data setup time t ds 20 ? ns data transfer from cell to register t r ?25s output high-z to re# low t ir 0?ns read cycle time t rc 45 ? ns re# access time t rea ?30ns re# high hold time t reh 15 ? ns re# high to output hold t rhoh (3) 15 ? ns re# high to we# low t rhw 100 ? ns re# high to output high-z t rhz ? 100 ns re# low to output hold t rloh (5) ??ns re# pulse width t rp 25 ? ns ready to re# low t rr 20 ? ns device resetting time (read/program/erase) t rst ? 5/10/500 (2) s we# high to busy t wb ? 100 ns write cycle time t wc 45 ? ns we# high hold time t wh 15 ? ns we# high to re# low t whr 60 ? ns we# pulse width t wp 25 ? ns write protect time t ww 100 ? ns document number: 002-00330 rev. *k page 35 of 71 S34MS01G1 s34ms02g1 s34ms04g1 5.5 dc characteristics notes: 1. all v ccq and v cc pins, and v ss and v ssq pins respectively are shorted together. 2. values listed in this table refer to the complete voltage range for v cc and v ccq and to a single device in case of device stacking. 3. all current measurements are performed with a 0.1 f capacitor connected between the v cc supply voltage pin and the v ss ground pin. 4. standby current measurement can be performed after the device has completed the initialization process at power up. refer to section 4.1 for more details. 5.6 pin capacitance note: 1. for the stacked devices version the input is 10 pf x [number of stacked chips] and the input/output is 10 pf x [number of sta cked chips]. table 5.5 dc characteristics and operating conditions parameter symbol test conditions min typ max units power-on current (s34ms02g1, s34ms04g1) i cc0 power-up current (refer to section 4.1 ) ?1530ma operating current sequential read i cc1 t rc = see table 5.4 ce#=v il , i out = 0 ma ?1020ma program i cc2 normal ( S34MS01G1) ?1020ma normal (s34ms02g1) ?1020ma normal (s34ms04g1) ??20ma cache (s34ms02g1) ?1530ma cache (s34ms04g1) ??30ma erase i cc3 ? (S34MS01G1) ?1020ma ? (s34ms02g1) ??20ma ? (s34ms04g1) ?1020ma standby current, (ttl) i cc4 ce# = v ih , wp# = 0v/vcc ?? 1ma standby current, (cmos) i cc5 ce# = v cc ?0.2, wp# = 0/v cc ?1050a input leakage current i li v in = 0 to 3.6 v ? ? 10 a output leakage current i lo v out = 0 to 3.6 v ? ? 10 a input high voltage v ih ?v cc x 0.8 ? v cc + 0.3 v input low voltage v il ?-0.3?v cc x 0.2 v output high voltage v oh i oh = -100 a v cc ?0.1 ? ? v output low voltage v ol i ol = 100 a 0.1 v output low current (r/b#) i ol(r/b#) v ol = 0.1 v 3 4 ? ma v cc supply voltage (erase and program lockout) v lko ??1.1?v table 5.6 pin capacitance (ta = 25 c, f=1.0 mhz) parameter symbol test condition min max unit input c in v in = 0 v ? 10 pf input / output c io v il = 0 v ? 10 pf document number: 002-00330 rev. *k page 36 of 71 S34MS01G1 s34ms02g1 s34ms04g1 5.7 program / erase characteristics notes: 1. typical program time is defined as the time within which more than 50% of the whole pages are programmed (v cc = 1.8 v, 25 c). 2. copy back read and copy back program for a given plane must be between odd address pages or between even address pages for th e device to meet the program time (t prog ) specification. copy back program may not meet this specific ation when copying from an odd address page (source page) to an ev en address page (target page) or from an even address page (source page) to an odd address page (target page). table 5.7 program / erase characteristics parameter description min typ max unit program time / multiplane program time (2) t prog ? 250 700 s dummy busy time for multiplane program ( s34ms02g1, s34ms04g1) t dbsy ?0.5 1 s cache program short busy time ( s34ms02g1, s34ms04g1) t cbsyw ?5t prog s number of partial program cycles in the same page main + spare nop ? ? 4 cycle block erase time / multiplane erase time ( s34ms02g1, s34ms04g1) t bers ?3.510ms block erase time ( S34MS01G1) t bers ?2 3ms read cache busy time t cbsyr ?3t r s document number: 002-00330 rev. *k page 37 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6. timing diagrams 6.1 command latch cycle command input bus operation is used to give a command to the me mory device. commands are accepted with chip enable low, command latch enable high, address latch enable low, and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operatio n (write/ erase) the writ e protect pin must be high. figure 6.1 command latch cycle tcl s tcs twp command cle ce# we# ale i/ox tdh tds tals talh tclh tch = don?t care document number: 002-00330 rev. *k page 38 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.2 address latch cycle address input bus operation allows the insertion of the memory address. to insert the 27 (8 device) addresses needed to access the 1 gb, four write cycles are needed. addresses are accepted with chip enable low, address latch enable high, command latch enable low, and read enable high and latched on the rising edge of write enable. moreover, for commands that start a modify operation (write/ erase) the write protect pin must be high. figure 6.2 address latch cycle 6.3 data input cycle timing data input bus operation allows the data to be programmed to be sent to the device. the data insertion is serially, and timed b y the write enable cycles. data is accepted only with chip enable lo w, address latch enable low, command latch enable low, read enable high, and write protect high and latc hed on the rising edge of write enable. figure 6.3 input data latch cycle tcls tcs twc tals tals tals tals tals talh talh talh talh twc twc twc twp twp twh twp twp twh twh twh tds col. add1 cle ce# we# ale i/ox tds tds tds tds tdh tdh tdh tdh tdh col. add2 row. add2 row. add1 row. add3 talh = don?t care twc tclh tch twp twh din twh tdh tdh tdh tds tds tds twp twp cle ale ce# i/ox we# tals din 0 din final = don?t care document number: 002-00330 rev. *k page 39 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.4 data output cycle timing (c le=l, we#=h, ale=l, wp#=h) figure 6.4 data output cycle timing notes: 1. transition is measured at 200 mv from steady state voltage with load. 2. this parameter is sampled and not 100% tested. 3. t rhoh starts to be valid when frequency is lower than 33 mhz. 6.5 data output cycle timing (edo type, cle=l, we#=h, ale=l) figure 6.5 data output cycle timing (edo) notes: 1. transition is measured at 200 mv from steady state voltage with load. 2. this parameter is sampled and not 100% tested. 3. t rloh is valid when frequency is higher than 33 mhz. 4. t rhoh starts to be valid when frequency is lower than 33 mhz. trc ce# re# i/ox r/b# trea trr t u o d t u o d t u o d trea trhz trea tchz tcoh trhoh treh trhz trc trp treh trea tcr trloh trr trea tchz tcoh trhz trhoh dout dout ce# re# i/ox r/b# = don?t care document number: 002-00330 rev. *k page 40 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.6 page read operation figure 6.6 page read operation (read one page) note: 1. if status register polling is used to determine completion of the read operation, the read command (00h) must be issued befor e data can be read from the page buffer. ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 30h dout n dout n +1 column address row address tcsd twb tclr tr trc trr busy tar dout m trhz twc = don?t care document number: 002-00330 rev. *k page 41 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.7 page read operation (interrupted by ce#) figure 6.7 page read operation interrupted by ce# ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 30h dout n dout n +1 column address row address tcsd twb tclr tr trc trr busy tar tchz tcoh dout n +2 = don?t care document number: 002-00330 rev. *k page 42 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.8 page read operation timing with ce# don?t care figure 6.8 page read operation timing with ce# don?t care 6.9 page program operation figure 6.9 page program operation note: 1. t adl is the time from the we# rising edge of final addr ess cycle to the we# rising edge of first data cycle. 00h col. add. 1 col. add. 2 row add. 1 row add. 2 dout n dout n + 1 = don?t care (v ih or v il ) ce# re# trea tcr ce# don?t care ce# cle ale we# re# i/ox 30h dout n + 2 dout n + 3 dout n + 4 dout n + 5 dout m dout m + 1 dout m + 2 r/b# tr trr trc i/ox dout row add. 3 cle ale ce# re# r/b# i/ox we# twc serial data input command column address row address read status command program command i/o0=0 successful program i/o0=1 error in program 1 up to m byte serial input din n din m twc twb tprog twhr twc tadl 80h col. add1 col. add2 row. add1 row. add2 h 0 7 h 0 1 i/o0 row. add3 = don?t care document number: 002-00330 rev. *k page 43 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.10 page program operation timing with ce# don?t care figure 6.10 page program operation timing with ce# don?t care 6.11 page program operat ion with random data input figure 6.11 random data input notes: 1. t adl is the time from the we# rising edge of final addr ess cycle to the we# rising edge of first data cycle. 2. for edc operation only one random data input is allowed at each edc unit. 80h col. add. 1 col. add. 2 row add. 1 row add. 2 din n din n + 1 din m din p din p + 1 din r 10h = don?t care ce# we# twp tcs tch ce# don?t care ce# cle ale we# re# i/ox row add. 3 cle ale ce# re# r/b# i/ox we# 80h din n din m din j din k 85h 10h 70h serial data input command random data input command column address column address serial input program command read status command tprog io0 twb col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 tadl row address twc twc tadl twc twhr = don?t care document number: 002-00330 rev. *k page 44 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.12 random data output in a page figure 6.12 random data output 6.13 multiplane page program operation ? s34ms02g1 and s34ms04g1 figure 6.13 multiplane page program notes: 1. any command between 11h and 81h is prohibited except 70h, 78h, and ffh. 2. a18 is the plane address bit for 8 devices. a17 is the plane address bit for 16 devices. ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 30h dout n dout n +1 05h col. add. 1 col. add. 2 dout m dout m +1 e0h column address row address column address tclr twhr trea twb tar trhw tr trc trr busy = don?t care cle ale ce# re# r/b# i/ox we# r/b# i/o0~7 ex.) address restriction for multiplane page program 81h 70h io program confirm command (true) tdbsy col add 1,2 and row add 1,2,3 (2112 byte data) a0 ~ a11: valid a12 ~ a17: fixed ?low? a18: fixed ?low? a19 ~ a28: fixed ?low? serial data input command column address page row address 1 up to 2112 byte data serial input program command (dummy) 11h 10h din n din m din n din m col. add1 80h col. add2 row add1 row add2 row add3 twb tprog twb tdbsy col. add1 col. add2 row add1 row add2 row add3 twc read staus command twhr tprog 80h address & data input 11h col add 1,2 and row add 1,2,3 (2112 byte data) a0 ~ a11: valid a12 ~ a17: valid a18: fixed ?high? a19 ~ a28: valid tadl tadl 81h address & data input 10h 70h (note 1) document number: 002-00330 rev. *k page 45 of 71 S34MS01G1 s34ms02g1 s34ms04g1 figure 6.14 multiplane page program (onfi 1.0 protocol) notes: 1. c1a-c2a column address for page a. c1a is the least significant byte. 2. r1a-r3a row address for page a. r1a is the least significant byte. 3. d0a-dna data to program for page a. 4. c1b-c2b column address for page b. c1b is the least significant byte. 5. r1b-r3b row address for page b. r1b is the least significant byte. 6. d0b-dnb data to program for page b. 7. the block address bits must be the same except for the bit(s) that select the plane. 6.14 block erase operation figure 6.15 block erase operation (erase one block) cmd addr addr addr addr addr cmd addr addr addr addr addr din din din din din din din din cmd cmd 80h c1 a c2 a d0 a r3 a r2 a r1 a d1 a ... dn a 11h 80h c1 b c2 b d0 b r3 b r2 b r1 b d1 b ... dn b 10h cycle type dqx sr[6] cycle type dqx sr[6] a tadl tadl tadl tipbsy tadl tprog twc ce# we# ale re# i/ox r/b# twb tbers busy auto block erase setup command i/o0=0 successful erase i/o0=1 error in erase row address d0h 60h 70h i/o0 erase command read status command row add1 row add2 row add3 twhr = don?t care document number: 002-00330 rev. *k page 46 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.15 multiplane block erase ? s34ms02g1 and s34ms04g1 figure 6.16 multiplane block erase note: 1. a18 is the plane address bit for 8 devices. a17 is the plane address bit for 16 devices. figure 6.17 multiplane block erase (onfi 1.0 protocol) notes: 1. r1a-r3a row address for block on plane 0. r1a is the least significant byte. 2. r1b-r3b row address for block on plane 1. r1b is the least significant byte. 3. the block address bits must be the same except for the bit(s) that select the plane. row address block erase setup command1 block erase setup command2 erase confirm command read status command busy row address ex.) address restriction for multiplane block erase operation ale cle ce# re# r/b# i/ox we# r/b# i/o0~7 twc 60h 60h row add1,2,3 row add1,2,3 a12 ~ a17 : fixed low a18 : fixed low a19 ~ a28 : fixed low a12 ~ a17 : fixed low a18 : fixed high a19 ~ a28 : valid address address h 0 7 h 0 6 d0h h 0 d h 0 6 70h i/o0 row add1 row add1 row add2 row add2 3 d d a w o r 3 d d a w o r twc twb tbers tbers twhr i/o 1 = 0 successful erase i/o 1 = 1 error in plane 60h cle we# ale re# iox r1 a r2 a r3 a d1h 60h r1 b r2 b sr[6] t iebsy r3 b d0h t bers document number: 002-00330 rev. *k page 47 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.16 copy back read wi th optional data readout figure 6.18 copy back read with op tional data readout 6.17 copy back program oper ation with random data input figure 6.19 copy back program with random data input i/o r/b# busy tr (read busy time) busy tprog (program busy time) 00h source add inputs 35h data outputs 85h target add inputs 10h 70h/ 7bh sr0/ edc reg read status register/ edc register i/o r/b# busy tr (read busy time) busy tprog (program busy time) 00h source add inputs 35h 85h 2 cycle add inputs 10h unlimited number of repetitions 70h sr0 read status register 85h target add inputs data data document number: 002-00330 rev. *k page 48 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.18 multiplane copy back progr am ? s34ms02g1 and s34ms04g1 figure 6.20 multiplane copy back program notes: 1. copy back program operation is allowed only within the same memory plane. 2. any command between 11h and 81h is prohibited except 70h, 78h, and ffh. 3. a18 is the plane address bit for 8 devices. a17 is the plane address bit for 16 devices. i/ox r/b# r/b# i/ox tr tr tdbsy tprog 1 1 00h add. (5 cycles) 35h col. add. 1, 2 and row add. 1, 2, 3 source address on plane 0 00h add. (5 cycles) 35h col. add. 1, 2 and row add. 1, 2, 3 source address on plane 1 85h add. (5 cycles) 11h col. add. 1, 2 and row add. 1, 2, 3 destination address a0 ~ a11 : fixed ?low? a12 ~ a17 : fixed ?low? a18 : fixed ?low? a19 ~ a28 : fixed ?low? 81h add. (5 cycles) col. add. 1, 2 and row add. 1, 2, 3 destination address a0 ~ a11 : fixed ?low? a12 ~ a17 : valid a18 : fixed ?high? a19 ~ a28 : valid 10h 70h plane 0 (1) (3) data field spare field plane 1 (2) (3) data field spare field source page source page target page target page (1) : copy back read on plane 0 (2) : copy back read on plane 1 (3) : multiplane copy back program (note 2) document number: 002-00330 rev. *k page 49 of 71 S34MS01G1 s34ms02g1 s34ms04g1 figure 6.21 multiplane copy back program (onfi 1.0 protocol) notes: 1. c1a-c2a column address for page a. c1a is the least significant byte. 2. r1a-r3a row address for page a. r1a is the least significant byte. 3. c1b-c2b column address for page b. c1b is the least significant byte. 4. r1b-r3b row address for page b. r1b is the least significant byte. 5. the block address bits must be the same except for the bit(s) that select the plane. 6.19 read status register timing figure 6.22 status / edc read cycle 85h cle we# ale re# iox c1 a c2 a r1 a r2 a r3 a 11h 85h c1 b c2 b sr[6] a t ipbsy r1 b r2 b r3 b 10h t prog tcls t clr t clh t cs t ch t wp t whr t cea t ds t rea t chz t coh t rhz t rhoh 70h or 7bh status output t dh t ir ce# we# i/ox cle re# = don?t care document number: 002-00330 rev. *k page 50 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.20 read status enhanced timing figure 6.23 read status enhanced timing 6.21 reset operation timing figure 6.24 reset operation timing cle ale we# i/o0-7 re# 78h r1 r2 sr r3 twhr tar ff t rst we# ale cle re# i/o7:0 r/b# document number: 002-00330 rev. *k page 51 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.22 read cache figure 6.25 read cache operation timing figure 6.26 ?sequential? read cache timing, start (a nd continuation) of cache operation page n page n page n + 1 page n + 2 page n + 1 page n + 3 page n + 2 page n + 3 data cache page buffer cell array page n page n + 1 page n + 2 page n + 3 1 1 2 3 3 4 5 5 6 7 7 8 9 ce# cle ale we# re# i/ox r/b# ce# cle ale we# re# i/ox r/b# a a 1 2 3 7 8 9 6 00h col. add 1 col. add 2 column address 00h row add 1 row add 2 page address n 30h 31h dout 0 dout 1 dout 31h dout 0 dout 1 col. add. 0 page n + 2 3fh dout 0 dout 1 dout 31h dout 0 dout dout 1 dout twc twb tr tcbsyr twb trr twb col. add. 0 page n col. add. 0 page n + 1 trc trc trr tcbsyr tcbsyr twb trr trc tcbsyr twb trr trc col. add. 0 page n + 3 = don?t care row add 3 4 5 5 cmd cmd dout dout dout cmd dout 0 d h 0 3 31h ... dn 31h d0 cycle type i/ox sr[6] trr as defined for read trr twb tr twb tcbsyr twb tcbsyr document number: 002-00330 rev. *k page 52 of 71 S34MS01G1 s34ms02g1 s34ms04g1 figure 6.27 ?random? read cache timing, start (and continuation) of cache operation figure 6.28 read cache timing, end of cache operation cycle type i/ox sr[6] cycle type i/ox sr[6] as defined for read a cmd addr addr addr addr twb tr a addr cmd 00h c1 c2 r1 r2 r3 31h cmd 30h dout dout dout d0 . . . dn page n page r cmd addr addr addr addr addr cmd 00h c1 c2 r1 r2 r3 31h dout d0 trr twb tcbsyr trr twb tcbsyr trr cycle type i/ox sr[6] as defined for read cache (sequential or random) dout dout dout cmd twb tcbsyr d0 . . . dn 3fh cmd 31h dout dout dout d0 . . . dn trr twb tcbsyr trr document number: 002-00330 rev. *k page 53 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.23 cache program figure 6.29 cache program column address row address twb column address row address tcbsyw 1 1 cle ale ce# re# r/b# i/ox we# tcbsyw din n din m din n din m column address row address 10h din n din m 70h tprog 80h col. add1 col. add2 row. add1 row. add2 row. add3 15h 80h 15h 80h col. add1 col. add2 row. add1 row. add2 row. add3 tadl twc col. add1 col. add2 row. add1 row. add2 row. add3 twc twc cle ale ce# re# r/b# i/ox we# status document number: 002-00330 rev. *k page 54 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.24 multiplane cache program ? s34ms02g1 and s34ms04g1 figure 6.30 multiplane cache program notes: 1. read status register (70h) is used in the figu re. read status enhanced (78h) can be also used. 2. a18 is the plane address bit for 8 devices. a17 is the plane address bit for 16 devices. cle ale ce# re# r/b# i/ox we# column address row address twb twc column address row address tcbsyw 1 1 tdbsy 80h col. add1 col. add2 row add1 row add2 row add3 81h col. add1 col. add2 row add1 row add2 row add3 15h din n din m 11h din n din m column address row address twc column address row address tprog tdbsy 11h din n din m 80h 81h col. add1 col. add2 row add1 row add2 row add3 10h din n din m twb tadl tadl twb 70h 80h address input data input 11h 81h address input data input 15h command input a13~a17: fixed ?low? a18: fixed ?low? a19~a31: fixed ?low? a13~a17: valid a18: fixed ?high? a19~a31: valid t dbsy return to 1 repeat a max of 63 times 80h address input data input 11h 81h address input data input 10h command input a13~a17: fixed ?low? a18: fixed ?low? a19~a31: fixed ?low? a13~a17: valid a18: fixed ?high? a19~a31: valid t dbsy t prog t cbsyw ry/by# ry/by# 1 1 cle ale ce# re# r/b# i/ox we# col. add1 col. add2 row add1 row add2 row add3 status document number: 002-00330 rev. *k page 55 of 71 S34MS01G1 s34ms02g1 s34ms04g1 figure 6.31 multiplane cache program (onfi 1.0 protocol) notes: 1. the block address bits must be the same except for the bit(s) that select the plane. 2. read status register (70h) is used in the figu re. read status enhanced (78h) can be also used. cle ale ce# re# r/b# iox we# column address row address twb twc column address row address tcbsyw 1 1 cle ale ce# re# r/b# iox we# tdbsy 11h din n din m 80h col. add1 col. add2 row add1 row add2 row add3 80h col. add1 col. add2 row add1 row add2 row add3 15h din n din m column address row address twc column address row address tprog tdbsy 11h din n din m 80h col. add1 col. add2 row add1 row add2 row add3 80h col. add1 col. add2 row add1 row add2 row add3 10h din n din m twb tadl tadl twb status 70h 80h address input data input 11h 80h address input data input 15h command input t dbsy return to 1 repeat a max of 63 times 80h address input data input 11h 80h address input data input 10h command input t dbsy t prog t cbsyw ry/by# ry/by# 1 1 document number: 002-00330 rev. *k page 56 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.25 read id operation timing figure 6.32 read id operation timing 6.26 read id2 operation timing figure 6.33 read id2 operation timing notes: 1. 4-cycle address is shown for the S34MS01G1. for s34ms02g1 and s34ms04g1, insert an additional address cycle of 00h. 2. if status register polling is used to determine completion of the read id2 operation, the read command (00h) must be issued b efore id2 data can be read from the flash. ce# we# cle re# ale twhr tar trea i/ox 01h a1h 00h 1dh 1 gb device i/ox 01h aah 90h 95h 2 gb device 44h i/ox 01h ach 90h 95h 4 gb device 54h read id command address 1 cycle maker code device code 3rd cycle 4th cycle 5th cycle 90h 90h 09h 00h 00h 00h ce# we# cle re# ale tr read id2 commands 4 cycle address 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle i/ox read id2 confirm command 30h 65h 00h 00h 02h 02h 00h 30h id2 data id2 data id2 data id2 data id2 data r/b# busy (note 1) document number: 002-00330 rev. *k page 57 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.27 read onfi signature timing figure 6.34 onfi signature timing 6.28 read parameter page timing figure 6.35 read parameter page timing note: 1. if status register polling is used to determine completion of the read operation, the read command (00h) must be issued befor e data can be read from the page buffer. 90h cle we# ale re# io0~7 20h 4fh t 4eh 46h whr 49h trea 00h cle we# ale re# io0-7 p1 r/b# ... ... t r 1 p0 1 p1 0 p0 0 ech document number: 002-00330 rev. *k page 58 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.29 otp entry timing figure 6.36 otp entry timing 6.30 power on and data protection timing figure 6.37 power on and data protection timing note: 1. v th = 1.2 volts. cle ale we# i/o0-7 29h 17h 19h 04h vcc v th vcc(min) 100 s max invalid 0v ce v il v operation 5 ms max ih v il wp ready/busy dont care dont care dont care vcc(min) v th document number: 002-00330 rev. *k page 59 of 71 S34MS01G1 s34ms02g1 s34ms04g1 6.31 wp# handling figure 6.38 program enabling / disabling through wp# handling figure 6.39 erase enabling / disabling through wp# handling t 80h 10h ww we# i/ox wp# r/b# t 80h 10h ww we# i/ox wp# r/b# t 60h d0h ww t 60h d0h ww we# i/ox wp# r/b# we# wp# r/b# i/ox document number: 002-00330 rev. *k page 60 of 71 S34MS01G1 s34ms02g1 s34ms04g1 7. physical interface 7.1 physical diagram 7.1.1 48-pin thin small outline package (tsop1) figure 7.1 ts/tsr 48 ? 48-pin plastic thin small outline, 12 x 20 mm, package outline 5006 \ f16-038 \ 6.5.13 package ts/tsr 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 o 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1994). 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of b dimension at max. material condition. dambar cannot be located on lower radius or the foot. minimum space between protrusion and an adjacent lead to be 0.07mm. 7. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 8. lead coplanarity shall be within 0.10mm as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads. document number: 002-00330 rev. *k page 61 of 71 S34MS01G1 s34ms02g1 s34ms04g1 7.1.2 63-pin ball grid array (bga) figure 7.2 vbm063 ? 63-pin bga, 11 mm x 9 mm package g5011\ 16-038.25 \ 6.5.13 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3, spp-020. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the total number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0. when there is an even number of solder balls in the outer row, sd = ed/2 and se = ee/2. 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbm 063 jedec m0-207(m) 11.00 mm x 9.00 mm nom package symbol min nom max note a --- --- 1.00 profile a1 0.25 --- --- ball height d 11.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 63 ball count b 0.40 0.45 0.50 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc. ball pitch sd 0.40 bsc. solder ball placement se 0.40 bsc. solder ball placement a3-a8,b2-b8,c1,c2,c9,c10 depopulated solder balls d1,d2,d9,d10,e1,e2,e9,e10 f1,f2,f9,f10,g1,g2,g9,g10 h1,h2,h9,h10,j1,j2,j9,j10 k1,k2,k9,k10 l3-l8,m3-m8 document number: 002-00330 rev. *k page 62 of 71 S34MS01G1 s34ms02g1 s34ms04g1 8. system interface to simplify system interface, ce# ma y be unasserted during data loading or sequential data reading as shown in figure 8.1 . by operating in this way, it is possible to connect nand flash to a microprocessor. figure 8.1 program operation with ce# don't care figure 8.2 read operation with ce# don't care ce# don?t care h 0 1 t u p n i a t a d (5 cycle) . d d a t r a t s h 0 8 data input cle ce# we# ale i/ox ce# don?t care h 0 3 h 0 0 cle ce# re# ale r/b# we# i/ox ) l a i t n e u q e s ( t u p t u o a t a d (5 cycle) . d d a t r a t s tr document number: 002-00330 rev. *k page 63 of 71 S34MS01G1 s34ms02g1 s34ms04g1 figure 8.3 page programming within a block page 63 page 31 page 2 page 1 page 0 page 63 page 31 page 2 page 1 page 0 (64) (32) (3) (2) (1) (64) (1) (3) (32) (1) data register data register from the lsb page to msb page data in : data (1) data (64) ex.) random page program (optional) data in : data (1) data (64) document number: 002-00330 rev. *k page 64 of 71 S34MS01G1 s34ms02g1 s34ms04g1 9. error management 9.1 system bad block replacement over the lifetime of the device, additional bad blocks may develo p. in this case, each bad block has to be replaced by copying any valid data to a new block. these additional bad blocks can be i dentified whenever a program or erase operation reports ?fail? i n the status register. the failure of a page program operation does not affect the data in other pages in the sa me block, thus the block can be replac ed by re-programming the current data and copying the rest of t he replaced block to an available valid block. refer to table 9.1 and figure 9.1 for the recommended procedure to follow if an error occurs during an operation. figure 9.1 bad block replacement notes: 1. an error occurs on the nth page of block a during a program operation. 2. data in block a is copied to the same location in block b, which is a valid block. 3. the nth page of block a, which is in controller buffer memory, is copied into the nth page of block b. 4. bad block table should be updated to prev ent from erasing or programming block a. table 9.1 block failure operation recommended procedure erase block replacement program block replacement read ecc (1 bit / 512+16 byte) data buffer memory of the controller n page ffh data ffh failure th n page th block a block b (1) (2) (3) document number: 002-00330 rev. *k page 65 of 71 S34MS01G1 s34ms02g1 s34ms04g1 9.2 bad block management devices with bad blocks have the sa me quality level and the same ac and dc characteristics as de vices where all the blocks are valid. a bad block does not affect the perfo rmance of valid blocks because it is isol ated from the bit line and common source l ine by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block informatio n is written prior to shipping. any block where the 1st byte in the s pare area of the 1st or 2nd or last page does not contain ffh i s a bad block. that is, if the first page has an ff value and should have been a non-ff value, then the non-ff value in the second page or the last page will indicate a bad block.the bad block information must be read before any erase is attempted, as the bad block information may be erased. for the system to be able to recognize the bad blocks ba sed on the original information, it is recommended to create a bad block table following the flowchart shown in figure 9.2 . the host is responsible to detect and track bad blocks, both factory bad blocks and blocks that may go bad during operation. once a block is found to be bad, data should n ot be written to that block.the 1st block, which is placed on 00h block address is guaranteed to be a valid block. figure 9.2 bad block management flowchart note: 1. check for ffh at the 1st byte in the spare area of the 1st, 2nd, and last pages. yes yes no no start block address= block 0 data =ffh? last block? end increment block address update bad block table (1) document number: 002-00330 rev. *k page 66 of 71 S34MS01G1 s34ms02g1 s34ms04g1 10. ordering information the ordering part number is formed by a valid combination of the following: valid combinations valid combinations list configurations planne d to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. notes: 1. bga package marking omits the leading ?s34? and the packing type designator from the ordering part number. 2. a, v, b: 4g 8 (00 in bus width) available. 3. S34MS01G1 @ 105c (v) and 105c gt-grade (b) needs 2-bit ecc / 512+16 bytes. s34ms 04g 1 00 t f i 00 0 packing type 0 = tray 3 = 13? tape and reel model number 00 = standard interface / onfi ( 8) 00 = standard interface ( 16) 01 = onfi ( 16) temperature range i = industrial (-40c to +85c) a = industrial with aecq-100 and gt grade (?40c to +85c) v = industrial plus (?40c to + 105c) b = industrial plus with aecq-100 and gt grade (?40c to +105c) materials set f = pb-free h = pb-free low halogen package b=bga t = tsop bus width 00 = 8 nand, single die 04 = 16 nand, single die technology 1 = cypress nand revision 1 (4x nm) density 01g= 1 gb 02g= 2 gb 04g= 4 gb device family s34ms - 1.8v cypress slc nand flash memory for embedded valid combinations device family density technology bus width package type temperature range additional ordering options packing type package description s34ms 01g 1 00, 04 tf, bh i a (2) v, b (2)(3) 00, 01 0, 3 tsop, bga (1) 02g 04g document number: 002-00330 rev. *k page 67 of 71 S34MS01G1 s34ms02g1 s34ms04g1 11. document history document title: S34MS01G1/s 34ms02g1/s34ms04g1, 1-bit ecc, x8 and x16 i/o, 1.8v vcc slc nan d flash for embedded document number: 002-00330 rev. ecn no. orig. of change submission date description of change ** - xila 08/29/2012 initial release *a - xila 09/06/2012 48-pin tsop1 contact x8, x16 devices figure: corrected pinouts 63-vfbga contact, x16 device (balls down, top view) figure - corrected pinouts command set: reorganized section ac characteristics: corrected tals min and tds min *b - xila 10/01/2012 addressing: address cycle map ? 1 gb device: corrected data address cycle map ? 2 gb device - corrected data address cycle map ? 4 gb device -corrected data multiplane program ? s34ms02g1 and s34ms04g1: added tex block erase: added text multiplane block erase ? s34ms02g1 and s34ms04g1: added text copy back program: added text multiplane copy back program ? s34ms02g1 and s34ms04g1: added text multiplane cache program ? s34ms0 2g1 and s34ms04g1: added text multiplane page program operation ? s34ms02g1 and s34ms04g1: added note to multiplane page program figure added note to multiplane page program (onfi 1.0 protocol) figure multiplane block erase ? s34ms02g 1 and s34ms04g1: added note to multiplane block erase figure changed note to multiplane block erase (onfi 1.0 protocol) figure multiplane copy back program ? s34ms02g1 and s34ms04g1: added note to multiplane copy back program figure multiplane copy back program (onfi 1. 0 protocol) figure-corrected iox values, updated note multiplane cache program ? s34ms0 2g1 and s34ms04g1: added note to multiplane cache program figure multiplane cache program (onfi 1.0 protocol)- removed address values from ry/by# changed iox value from f1h to 70h updated note *c - xila 11/30/2012 absolute maximum ratings: absolute maximum ratings table- updated input or output voltage, and supply voltage values added note ac characteristics: ac characteristics table- updated values added note for tcoh and trhoh dc characteristics: dc characterist ics and operating conditions table- updated icc0, icc2, voh, and voh for S34MS01G1 ordering information: valid combinations table-updated additional ordering options document number: 002-00330 rev. *k page 68 of 71 S34MS01G1 s34ms02g1 s34ms04g1 *d - xila 12/19/2012 command set: added page reprogram command reorganized command set table page reprogram: moved section added paragraph copy back program: added paragraph reset: updated paragraph read id2: added text read parameter page: parameter page description table- fixed values of bytes 6-7 and 254-255 fixed description of bytes 129-130 and 131-132 dc characteristics: dc characterist ics and operating conditions table- power-on reset current (s34ml01g1): removed row operating current: removed icc1: trc = trc (min) input leakage current: removed vin = 0 to vcc (max) output leakage current: removed vo ut = 0 to vcc (max)output high voltage: removed ioh = 100 a, ioh = -400 a, and ioh = 400 a rows output low voltage: removed iol = 2.1 ma row output low current (r/b#): removed vol = 0.4v row ac characteristics: ac characteristics table-added note page read operation: page read op eration (read one page) figure- added note read id2 operation timing: read id2 operation timing figure- replaced twhr with tr and added r/b# timing signal added note bad block management: added text bad block management flowchart-updated note *e - xila 08/09/2013 global: data sheet designation updated from advance information to pre- liminary note that the s34ms04g1 is in the advanced information designation distinctive characteristics: security: removed serial number (unique id) operating temperature: removed co mmercial and extended temperatures performance: updated reliability general description: updated text removed bullets: readid2 extension and serial number (unique identifier) addressing: appended note in all address cycle map tables added text to bus cycle column in all address cycle map tables command set: command set table- added data to ?acceptable command during busy? column removed nth page entries changed status of cache program (end) and cache program (start) / (con- tinue) to ?supported on s34ml01g1? page read: updated text page program: added paragraph multiplane program ? s34ms02g1 and s34ms04g1: added paragraph document title: S34MS01G1/s 34ms02g1/s34ms04g1, 1-bit ecc, x8 and x16 i/o, 1.8v vcc slc nan d flash for embedded document number: 002-00330 rev. ecn no. orig. of change submission date description of change document number: 002-00330 rev. *k page 69 of 71 S34MS01G1 s34ms02g1 s34ms04g1 *e (continued) - xila 08/09/2013 page reprogram ? s34ms02g1 and s34ms04g1: added paragraph corrected page reprogram figure corrected page reprogram with data manipulation figure block erase: added paragraph multiplane block erase ? s34ms02g 1 and s34ms04g1: added paragraph copy back program: added paragraph multiplane copy back program ? s34ms02g1 and s34ms04g1: added paragraph read status register field definition: updated status register coding table cache program: added paragraph multiplane cache program ? s34ms0 2g1 and s34ms04g1: added para- graph read id: read id bytes table: updated description read parameter page: para meter page description table: corrected values for bits 6-7, 8-9, 129-130; bits 131-132; and bits 254-255 ready/busy: updated section updated ready/busy pin electrical application figure electrical characteristics: modified valid blocks table updated absolute maximum ratings table ac test conditions table: corrected output load cl value ac characteristics: ac characteristics table: added note data output cycle timing (cle=l, we #=h, ale=l, wp#=h): data output cycle timing figure: removed note multiplane page program operation ? s34ms02g1 and s34ms04g1: updated multiplane page program figure corrected multiplane page program (onfi 1.0 protocol) figure copy back read with optional data readout: corrected copy back read with optional data readout figure copy back program operation with random data input: modified copy back program operation with random da ta input figure, read status reg- ister timing: status / edc read cycle figure: removed note, removed read status enhanced cycle figure, read cache: updated read cache operation timing figure, removed cache timing heading cache program: cache program figure: corrected i/ox timing multiplane cache program ? s34ms0 2g1 and s34ms04g1:multiplane cache program figure: corrected i/ox timing multiplane cache program (onfi 1.0 pr otocol) figure: corrected i/ox timing read id operation timing: read id operation timing figure: corrected device code data, read parameter page timing: added note to read parameter page timing figure, one-time programmable (otp) entry: added note stating that the otp feature in the S34MS01G1 does not have nonvolatile protection physical interface: updated figures: ts/tsr 48 ? 48-lead plastic thin small outline, 12 x 20 mm, package outline vbm063 ? 63-pin bga, 11 mm x 9 mm package system interface: updated read op eration with ce# don't care figure ordering information: clarified materials set: h = lead (pb)-free and low halogen added note to valid combinations table *f - xila 06/24/2014 global : added automotive temperature option *g - xila 10/28/2014 global: data sheet designatio n updated from preliminary to full production document title: S34MS01G1/s 34ms02g1/s34ms04g1, 1-bit ecc, x8 and x16 i/o, 1.8v vcc slc nan d flash for embedded document number: 002-00330 rev. ecn no. orig. of change submission date description of change document number: 002-00330 rev. *k page 70 of 71 S34MS01G1 s34ms02g1 s34ms04g1 . *h 4955758 xila 10/15/2015 updated to cypress template. *i 5260112 xila 05/09/2016 updated distinctive characteristics : replaced ?automotive? wit h ?industrial plus? under ?operating temperature?. updated command set : updated read parameter page : updated description. updated ordering information : updated definitions for ?a?, ?v? and ?b? under ?temperature range?. updated to new template. *j 5409174 xila 08/30/2016 updated reliability features in performance . *k 5246984 aesatmp7 04/20/2017 update d cypress logo and copyright. document title: S34MS01G1/s 34ms02g1/s34ms04g1, 1-bit ecc, x8 and x16 i/o, 1.8v vcc slc nan d flash for embedded document number: 002-00330 rev. ecn no. orig. of change submission date description of change document number: 002-00330 rev. *k revised april 20, 2017 page 71 of 71 ? cypress semiconductor corporation, 2012-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desig n, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. 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